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87951ayi www.idt.com rev. c july 17, 2010 1 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer g eneral d escription f eatures the ics87951i is a low voltage, low skew 1-to-9 differential-to-lvcmos/lvttl cock generator. the cs87951i has two selectable clock inputs. the single ended clock input accepts lvcmos or lvttl input levels. the clk1, nclk1 pair can accept most standard differential input levels. with output frequencies up to 180mhz, the ics87951i is targeted for high performance clock appli- cations. along with a fully integrated pll, the ics87951i con- tains frequency configurable outputs and an external feedback input for regenerating clocks with ?zero delay?. ? fully integrated pll ? nine single ended 3.3v lvcmos/lvttl outputs ? selectable single ended clk0 or differential clk1, nclk1 inputs ? the single ended clk0 input can accept the following input levels: lvcmos or lvttl input levels ? clk1, nclk1 supports the following input types: lvds, lvpecl, lvhstl, sstl, hcsl ? output frequency range: 25mhz to 180mhz ? vco range: 200mhz to 480mhz ? external feedback for ?zero delay? clock regeneration ? cycle-to-cycle jitter: 100ps (typical) ? output skew: 375ps (maximum) ? pll reference zero delay: 350ps window (maximum) ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages p in a ssignment qd2 v ddo qd3 gnd qd4 v ddo mr/noe nclk1 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 qc0 v ddo qc1 gnd qd0 v ddo qd1 gnd v dda ext_fb div_sela div_selb div_selc div_seld gnd clk1 gnd qb v ddo qa gnd clk0 pll_sel clk_sel ics87951i 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view
87951ayi www.idt.com rev. c july 17, 2010 2 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer b lock d iagram div_sela pll_sel clk0 clk_sel nclk1 clk1 ext_fb div_selb div_selc mr/noe div_seld qa qb qc0 qc1 qd0 qd1 qd2 qd3 qd4 0 1 0 1 0 1 0 1 1 0 0 1 vco 200-480mhz phase detector lpf 2 4 8 internal pulldown internal pulldown internal pullup internal pulldown internal pulldown internal pulldown internal pulldown internal pulldown internal pulldown internal pulldown/ pullup power-on reset
87951ayi www.idt.com rev. c july 17, 2010 3 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v a d d r e w o p. n i p y l p p u s g o l a n a 2b f _ t x et u p n ip u l l u p h t i w s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l . " y a l e d o r e z " 3a l e s _ v i dt u p n in w o d l l u p . d 3 e l b a t n i d e b i r c s e d s a t u p t u o a k n a b r o f e u l a v e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4b l e s _ v i dt u p n in w o d l l u p . d 3 e l b a t n i d e b i r c s e d s a t u p t u o b k n a b r o f e u l a v e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5c l e s _ v i dt u p n in w o d l l u p . d 3 e l b a t n i d e b i r c s e d s a s t u p t u o c k n a b r o f e u l a v e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 6d l e s _ v i dt u p n in w o d l l u p . d 3 e l b a t n i d e b i r c s e d s a s t u p t u o d k n a b r o f e u l a v e d i v i d s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 7 1 , 3 1 , 7 9 2 , 5 2 , 1 2 d n gr e w o p. d n u o r g y l p p u s r e w o p 81 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 91 k l c nt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 0 1e o n / r mt u p n in w o d l l u p c i g o l n e h w . e l b a n e t u p t u o w o l e v i t c a . t e s e r r e t s a m h g i h e v i t c a d e t a t s - i r t e r a s t u p t u o e h t d n a t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . ) z i h ( . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e , 5 1 , 1 1 7 2 , 3 2 , 9 1 v o d d r e w o p. s n i p y l p p u s t u p t u o , 4 1 , 2 1 0 2 , 8 1 , 6 1 , 3 d q , 4 d q 0 d q , 1 d q , 2 d q t u p t u o 7 . s t u p t u o k c o l c d k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 2 , 2 20 c q , 1 c qt u p t u o 7 . s t u p t u o k c o l c c k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 6 2b qt u p t u o 7 . t u p t u o k c o l c b k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 2a qt u p t u o 7 . t u p t u o k c o l c a k n a b . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 30 k l ct u p n in w o d l l u p. t u p n i k c o l c e c n e r e f e r r o t c e t e d e s a h p l t t v l / s o m c v l 1 3l e s _ l l pt u p n in w o d l l u p e h t o t t u p n i e h t s a k c o l c e c n e r e f e r e h t d n a l l p e h t n e e w t e b s t c e l e s e c n e r e f e r e h t s t c e l e s , w o l n e h w . l l p s t c e l e s , h g i h n e h w . s r e d i v i d . k c o l c. s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 3l e s _ k l ct u p n in w o d l l u p , w o l n e h w . 0 k l c s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 1 k l c n , 1 k l c s t c e l e s : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p ) t u p t u o r e p ( e c n a t i c a p a c n o i t a p i s s i d r e w o pv a d d v , o d d v 7 4 . 3 =5 2f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o 57 2 1
87951ayi www.idt.com rev. c july 17, 2010 4 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer t able 3a. o utput c ontrol p in f unction t able s t u p n is t u p t u o e o n / r ma qb q1 c q , 0 c q4 d q : 0 d q 1z i hz i hz i hz i h 0d e l b a n ed e l b a n ed e l b a n ed e l b a n e t able 3b. o perating m ode f unction t able s t u p n i e d o m g n i t a r e p o l e s _ l l p 0s s a p y b 1l l p t able 3c. pll i nput f unction t able s t u p n i l e s _ k l ct u p n i l l p 01 k l c n , 1 k l c 10 k l c s t u p n is t u p t u o a l e s _ v i db l e s _ v i dc l e s _ v i dd l e s _ v i da qb qx c qx d q 0000 2 / o c v4 / o c v4 / o c v4 / o c v 000 1 2 / o c v4 / o c v4 / o c v8 / o c v 00 10 2 / o c v4 / o c v8 / o c v4 / o c v 00 11 2 / o c v4 / o c v8 / o c v8 / o c v 0100 2 / o c v8 / o c v4 / o c v4 / o c v 0101 2 / o c v8 / o c v4 / o c v8 / o c v 0110 2 / o c v8 / o c v8 / o c v4 / o c v 0111 2 / o c v8 / o c v8 / o c v8 / o c v 10 0 0 4 / o c v4 / o c v4 / o c v4 / o c v 10 0 1 4 / o c v4 / o c v4 / o c v8 / o c v 10 10 4 / o c v4 / o c v8 / o c v4 / o c v 10 1 1 4 / o c v4 / o c v8 / o c v8 / o c v 1100 4 / o c v8 / o c v4 / o c v4 / o c v 110 1 4 / o c v8 / o c v4 / o c v8 / o c v 1110 4 / o c v8 / o c v8 / o c v4 / o c v 1111 4 / o c v8 / o c v8 / o c v8 / o c v t able 3d. p rogrammable o utput f requency f unction t able
87951ayi www.idt.com rev. c july 17, 2010 5 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer t able 4b. dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c t able 4a. p ower s upply dc c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i o d d t n e r r u c y l p p u s r e w o pv l l a d d s n i p5 1 1a m i a d d t n e r r u c y l p p u s g o l a n a 0 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 0 k l c2v d d 3 . 0 +v , d l e s _ v i d : a l e s _ v i d , l e s _ k l c , l e s _ l l p e o n / r m , b f _ t x e 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 0 k l c3 . 0 -3 . 1v , d l e s _ v i d : a l e s _ v i d , l e s _ k l c , l e s _ l l p e o n / r m , b f _ t x e 3 . 0 -8 . 0v v p p k a e p - o t - k a e p e g a t l o v t u p n i 1 k l c n , 1 k l c0 0 30 0 0 1v m v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0 + d n gv d d 5 8 . 0 -v v h o e g a t l o v h g i h t u p t u oi h o a m 0 4 - =4 . 2v v l o e g a t l o v w o l t u p t u oi l o a m 0 4 =5 . 0v i n i t n e r r u c t u p n i 0 2 1 a v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i 1 k l c n d n a 1 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n a d d . v 3 . 0 + a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dda + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 42.1c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
87951ayi www.idt.com rev. c july 17, 2010 6 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer t able 6. ac c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o a q 20 8 1z h m b q / a q 40 2 1z h m b q 80 6z h m f o c v e g n a r k c o l o c v l l p0 0 20 8 4z h m ) ? ( t ; t e s f f o e s a h p c i t a t s 3 , 1 e t o n 0 k l c z h m 0 5 = f e r f , k c a b d e e f8 / o c v = 5 8 1 -5 15 6 1s p , 1 k l c 1 k l c n 5 4 4 -5 6 2 -5 9 -s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o s e i c n e u q e r f e m a s5 7 3s p s e i c n e u q e r f t n e r e f f i d f a q x a m z h m 0 5 1 < f a q x a m z h m 0 5 1 > 0 0 5 0 5 7 s p s p t ) c c ( t i j3 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 0 1 s p t k c o l 3 e t o n ; e m i t k c o l l l p 0 1s m t r e m i t e s i r t u p t u ov 2 o t 8 . 01 . 00 . 1s n t f e m i t l l a f t u p t u ov 2 o t 8 . 01 . 00 . 1s n t w p h t d i w e s l u p t u p t u o0 0 0 1 - 2 / e l c y c t0 0 0 1 + 2 / e l c y c ts p t l z p e m i t e l b a n e t u p t u o 6s n t z l p t , z h p e m i t e l b a s i d t u p t u o 7s n t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u , l a n g i s t u p n i k c a b d e e f d e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 1 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n t able 5. pll i nput r eference c haracteristics , v dda = v ddo = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f f e r y c n e u q e r f e c n e r e f e r t u p n i 0 0 1z h m
87951ayi www.idt.com rev. c july 17, 2010 7 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer p arameter m easurement i nformation 3.3v o utput l oad ac t est c ircuit d ifferential i nput l evel o utput s kew c ycle - to -c ycle j itter o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime t jit(cc) = t cycle n ? t cycle n+1 1000 cycles p hase j itter and s tatic p hase o ffset scope qx lvcmos 1.65v5% -1.65v5% qa, qb, qcx, qdx ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t sk(o) v ddo 2 v ddo 2 qy qx v cmr cross points v pp gnd clk1 nclk1 v dd clock outputs 0.8v 2v 2v 0.8v t r t f ext_fb ? ? t (?) v oh v ol v oh v ol v ddo 2 clk0, clk1 nclk1 t pw t period v ddo 2 v ddo 2 v ddo 2 t pw t period odc = qa, qb, qcx, qdx v dda , v ddo gnd (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t (?) mean = static phase offset t jit(?) = t (?) ? t (?) mean = phase jitter
87951ayi www.idt.com rev. c july 17, 2010 8 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics87951i provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dda and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd w iring the d ifferential i nput to a ccept s ingle e nded l evels v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609.
87951ayi www.idt.com rev. c july 17, 2010 9 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer f igure 3c. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk1 /nclk1 accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4d show interface examples for the clk1/nclk1 input driven by the most common driver types. the input interfaces suggested f igure 3a. clk/ n clk i nput d riven by lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v i nputs : clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. we recommend that there is no trace attached.
87951ayi www.idt.com rev. c july 17, 2010 10 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer t ransistor c ount the transistor count for ics87951i is: 2674 t able 7. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. r eliability i nformation
87951ayi www.idt.com rev. c july 17, 2010 11 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer p ackage o utline - y s uffix for 32 l ead lqfp t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
87951ayi www.idt.com rev. c july 17, 2010 12 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated device technology, inc. ( idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are i mplied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other extraordinary environmental requirement s are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use i n life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i y a 1 5 9 7 8i y a 1 5 9 7 8 s c ip f q l d a e l 2 3e b u tc 5 8 o t c 0 4 - t i y a 1 5 9 7 8i y a 1 5 9 7 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l i y a 1 5 9 7 8l i y a 1 5 9 7 8 s c ip f q l " e e r f - d a e l " d a e l 2 3e b u tc 5 8 o t c 0 4 - t f l i y a 1 5 9 7 8l i y a 1 5 9 7 8 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o t i a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a r a h t s t r a p : e t o n
87951ayi www.idt.com rev. c july 17, 2010 13 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b 1 t 2 t 3 3 5 8 9 . n o i t p i r c s e d e o n / r m d e s i v e r - e l b a t n o i t p i r c s e d n i p c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 r d e d d a t u o . w o r v d e g n a h c - s c i t s i r e t c a r a h c c d h i v o t x a m v 6 . 3 m o r f 0 k l c d d d n a v 3 . 0 + v d e d d a l i . w o r 0 k l c . m a r g a i d t u p n i l a i t n e r e f f i d g n i v i r d l a n g i s d e d n e e l g n i s d e t a d p u . n o i t c e s e c a f r e t n i t u p n i k l c n / k l c d e d d a 3 0 / 0 1 / 7 9 t 1 9 2 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . e t o n d n a , g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 3 2 / 1 1 c9 t2 1 4 1 . s c i m o r f t d i h t i w r e t o o f / r e d a e h s ' t e e h s a t a d d e t a d p u . n m u l o c r e b m u n r e d r o / t r a p m o r f x i f e r p s c i d e v o m e r . e g a p t c a t n o c d e d d a 0 1 / 7 1 / 7
87951ayi www.idt.com rev. c july 17, 2010 14 ics87951i l ow s kew , 1- to -9 d ifferential - to -lvcmos/lvttl z ero d elay b uffer we?ve got your timing solution. sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 tech support netcom@idt.com 6024 silver creek valley road san jose, ca 95138 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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